Dr. Francisco J. Cazorla is the leader of the group on Interaction between the Operating System and the Computer Architecture (CAOS) at BSC. He has worked in industry projects with several processor vendor companies (Intel, IBM, and Sun Microsystems (ORACLE)), projects with the ESA as well as in FP6 (SARC) and FP7 Projects (MERASA, parMERASA, VeTeSS). He has led two industrial projects, one with IBM and one with Sun Microsystems on power and performance characterization of multicore processors. He has also led the EU projects PROARTIS and PROXIMA FP7 project on multicores contention. He is currently an ERC Consolidator Grant holder. He has coordinated 5 projects with the European Space Agency on timing analysis for multicores. As part of the PROARTIS, PROXIMA and one ESA project he has worked with avionics, railway, automotive, and space applications for their characterization and analysis of multicore architectures. He has also a long experience in working with real boards in critical and high-performance domains. Currently, Francisco participates in the European Processor Initiative (EPI) project together with Jaume Abella on the tailoring of the EPI processor for automotive needs.
Francisco J. Cazorla
Dr. Jaume Abella is a senior researcher in the CAOS group at BSC since 2009. He has a strong industrial background as he worked at Intel Corporation for more than 4 years (May-2005 till October-2009), where he co-authored 13 industrial patents and led several activities related to verification and testing of industrial processor designs, as well as on the design of memory hierarchies. He joined the BSC in 2009 where he has been in charge of activities related to the probabilistic analysis of real-time systems in FP7 PROXIMA (WP leader) and FP7 PROARTIS, and certification of critical real-time systems, such as those in automotive, avionics and space. In particular, Jaume led BSC certification activities in the industrial ARTEMIS VeTeSS project, and has been deeply involved in industrial use cases in H2020 SAFURE, FP7 PROXIMA and FP7 PROARTIS. Jaume also leads BSC work in H2020 RECIPE applying probabilistic analysis on HPC systems. In the hardware design front, Jaume leads BSC activities in H2020 De-RISC enhancing time predictability of a TRL8 RISC-V space and avionics multicore. Jaume also co-leads, together with Francisco, BSC work in the automotive stream of the H2020 European Processor Initiative (EPI) project and on the convergence of HPC and automotive needs. Jaume has received two HiPEAC tech transfer awards (2016 and 2017), and is co-author of a BSC patent on probabilistic-analysis amenable cache designs licensed to Cobham Gaisler. Jaume has coauthored more than 150 papers in top conferences and journals, and has supervised around 10 PhD and Master students.
Dr. Enrico Mezzetti is a senior Researcher in the CAOS group at the Barcelona Supercomputing Center (BSC). He holds a PhD in Computer Science obtained in 2012 at the University of Bologna (Italy) and p[partially funded by Thales Alenia Space - France, with a work on cache-aware timing analysis and industrial development process. Enrico research interests touch several aspects of the analysis and design of embedded real-time systems (from timing analysis, to scheduling and resource-sharing protocols), specializing in industrial-size, complex, high-criticality software systems. More recently, Enrico has been continuing his research on analysis and development of real-time and embedded systems, with a main focus on measurement-based deterministic and probabilistic timing analysis techniques for analyzing the timing behavior of multi-core and many-core real-time embedded systems. On the same topic he participated to two large collaborative FP7 projects on measurement-based probabilistic timing analysis, PROARTIS and PROXIMA. Throughout his academic curriculum he has been participating (occasionally as WP leader) in a number of medium-large scale collaborative EU projects (FP and ESA) with an exceptional level of industrial participation. Enrico gathered a fair experience in teaching (BSc and doctorate level courses) and mentoring graduate and undergraduate students in the topics of timing analysis (deterministic and probabilistic), empirical evaluation of multicore scheduling algorithms and protocols, and RTOS design. Enrico has coauthored more than 50 papers in top-tier conferences and journals in the field of embedded real-time systems and timing analysis, such as RTSS, ECRTS, DAC, DATE, RTAS, RTCSA, EMSOFT, SAC, IEEE Micro, IEEE D&T. In 2017, he has been awarded a Juan de la Cierva post-doctoral grant by the Spanish Ministry of Economy and Competitiveness, to conduct research on novel approaches to the timing analysis of COTS platforms.
Dr. Hamid Tabani is a senior researcher in the CAOS group at BSC. He holds a Ph.D. in the area of Computer Architecture from Universitat Politècnica de Catalunya (UPC) with a mark of Excellent Cum Laude. In his current position in the CAOS group, he is participating in several national, industrial and European projects such as ERC SuPerCom and European Processor Initiative (EPI) on the topics of computer architecture, autonomous driving, and safety-critical systems. He is the responsible researcher for topics related to deep learning, neural networks and autonomous driving where he contributes to several projects and supervises students and research engineers. He has worked on several projects to propose and design low-power hardware architectures for cognitive computing applications based on machine learning. He proposed several techniques to improve the performance and energy efficiency of application based on deep learning and neural networks at software, microarchitecture, and hardware level. He has several publications in top-tier conferences and journals (HPCA, DAC, PACT, IEEE Micro, IEEE Transactions) where he published part of his main contributions and he has won several awards from HiPEAC, IEEE Technical Committee on Computer Architecture (TCCA), European Design Automation Association (EDAA), the ACM Special Interest Group on Design Automation (SIGDA), and the IEEE Council on Electronic Design Automation (CEDA).
Dr. Isabel Serra is a mathematician and a senior researcher in the CAOS group at BSC and also a postdoctoral researcher at the complex systems research group of the Centre for Mathematical Research (CRM) from Universitat Autònoma de Barcelona (UAB). She has worked on the development of methods for extreme value prediction applied to Computer Science and Earth Science to precisely and reliably predicts extreme events. She holds a PhD (excellent cum laude) in the area of risk model at Universitat Autònoma de Barcelona (UAB). She proposed several techniques for improving the theoretical results in extreme value theory for statistical modeling in several real frames of application: finance, environmental and complex systems. In Computer Science, her work has focused on predicting high execution times for critical real-time systems using a risk analysis and survivability analysis. Her junior postdoctoral stage was carried out in Centre de Recerca Matemàtica on physical statistic problems. Overall, the academic trajectory was combined with several collaborations in projects with a private and public institution. This background led her to get a stable position at CRM as Head of knowledge and technology transfer advisor unit. The most recent works were developing as a principal researcher in a machine learning project with Zurich Insurance group. She is advising on the transfer technology on microfluids mechanic for creating a spin-off with World Mobile Capital and she is a professor in the data science course of Coursera ordered by UAB. Currently, at BSC, she works on the statistical analysis of deep learning-based workloads in safety-critical domains such as autonomous driving.
Sergi Vilardell Moreno is a PhD student at the Computer Architecture and Operating Systems group in Barcelona Supercomputing Center. His background is in Physics and Applied Mathematics, which helps to apply advanced statistic tools to improve Timing Analysis techniques. Currently, his line of research is focused on Extreme Value Theory applied to execution time traces of embedded critical systems. His main interests are Statistics, Machine Learning, and Computer Science.
Sergi Vilardell Moreno
Pedro Benedicte is a PhD candidate at the Computer Architecture Department of Universitat Politécnica de Catalunya (UPC) and a resident student at Barcelona Supercomputing Center (BSC). He received a MSc in innovation and research in informatics from UPC in 2016. His research focuses on architectures for Real-Time Systems and Probabilistic Timing Analysis.
David Trilla Rodríguez is a PhD candidate for the CAOS group in the Barcelona Supercomputing Center (BSC). He obtained his M.S. degree in 2016 and graduated in Informatics Engineering in 2014, both titles obtained from the Universitat Politècnica de Catalunya. He enrolled BSC in 2014 and has participated in the European project ESA-HAIR working on timing prediction models of real-time software for multicore processors during early design stages. His current research focuses on the impact of energy consumption, security, and reliability in time randomized architectures.
David Trilla Rodríguez
Javier E. Barrera Herrera is a Master Student at the Computer Architecture and Operating Systems group in Barcelona Supercomputing Center. His background is in Informatics with a mention in Computer Engineering, which helps to analyze embedded critical real-time systems. Currently, his line of research is focused on Timing Analysis/Characterizations of High-Performance GPUs/CPUs.
Javier E. Barrera Herrera
Miguel Alcón Doganoc is a Master student at the Computer Architecture and Operating Systems group in Barcelona Supercomputing Center. His studies in Computer Science specialized in Advanced Computing, guides him in his current line of research: the analysis of autonomous driving frameworks and their resource usage testing. Miguel's main interests are parallel computing, artificial intelligence, and robotics.
Miguel Alcón Doganoc
Jeremy J. Giesen León is a master student of the degree in Innovation and Research in Informatics (MIRI) in the specialization of high-performance computing at the Universitàt Politécnica de Catalunya (UPC). He enrolled the Computer Architecture and Operating System group at Barcelona Supercomputing Center in 2018 where he is currently working in his current research line: bounding the interference of multicore hardware contention on the non-functional behavior of applications. His undergraduate in computer engineering enables him to analyze the different micro-architectures, specially for embedded processors, to develop and push forward his research line.
Jeremy J. Giesen León
Roger Pujol Torramorell is a Master student at the Computer Architecture and Operating Systems (CAOS) group in the Barcelona Supercomputing Center (BSC). His current research lines are hardware simulation and modeling, autonomous driving and embedded systems benchmarking. He is currently studying a Master degree in Innovation and Research in Informatics (MIRI) in the specialization of Advanced Computing at the Universitat Politècnica de Catalunya (UPC). Roger's main interests include artificial intelligence, parallel computing, and high-performance computing.